Today, complex integrated circuits are sometimes designed in software, and then translated from a software description into a hardware description. Two software tools are typically used to do this translation, namely, a “component generator” and a “netlister”.
A component generator is a mechanism that, when given parameters describing an electronic component, generates a version of the component itself. Examples of components that might be generated include multipliers, finite impulse response (FIR) filters, counters, and fast Fourier transforms (FFTs). The parameters specify the characteristics the component should have. For example, if the component is to be a multiplier, the parameters might specify the latency, maximum width, and the algorithm to be employed. The CoreGen tool, supplied by Xilinx, Inc. of San Jose, Calif., is an example of a component generator.
A netlister is a mechanism that translates portions of an electronic design from a high-level representation into a lower-level one. For example, in the high-level modeling system known as System Generator from by Xilinx, Inc. of San Jose, Calif., a netlister is employed to translate user designs into VHDL. The job of translation is often split between a netlister and a component generator. In System Generator, for example, some translation is done by CoreGen, and the remainder is done by the System Generator netlister.
Use of component generators is widespread, as they simplify the job of generating complicated or large components. However, component generators may be slow and use a substantial amount of memory.
The relatively long execution time and high memory cost of component generators is due in part to the size and complicated nature of some components. Continuing the example of multipliers, there are many algorithms from which to select and many parameters to specify to arrive at a particular multiplier. Moreover, a large multiplier can be complicated and require many connections.
The set of all possible configurations of a component is often enormous, making it impractical to provide compiled versions of every possible combination. An individual designer, however, often uses the same component configuration more than once. Conventionally, each use of a generated component involves a compilation, even if the component has previously been compiled.
Another problem contributing to long running times for component generators is the number of components in a design. Designs are becoming more complicated, and conventional software tools for implementing complex designs may have difficulty or be limited in the size of design they can handle due at least in part to the volume of compilation to be done. Users may use the same component in multiple locations in a design. In practice, this may be done by copying and pasting a component from one logic block into another logic block. However, this means that the same component is compiled more than once. This redundancy in compilation may be a limiting factor with respect to design size, as well as cause an increase in compilation time.
In large electronic designs, portions of the design may have been replicated many times with only minor variations. Classically, a netlister generates a separate Hardware Description Language (“HDL”) object (e.g., a VHDL entity or Verilog module) for each copy, even though it may be possible to reuse a previously generated object. There would be a substantial advantage to reusing HDL objects, because reuse would reduce run time and memory requirements of downstream tools such as synthesis engines.
Accordingly, it would be desirable and useful to allow a component generator to recognize when a component has been previously generated so it can be reused. Additionally, it would be desirable and useful to allow a netlister to recognize when a previously generated HDL object can be reused.